To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required.

Task 2: Single-phase half-wave phase-controlled rectifier with RL load Recall Chapter 2, Make a new project. Build a single-phase half-wave phase-controlled rectifier with RL load Use the sinusoidal source in the SOURCE lib set amplitude 450V and frequency 20Hz Use the pulse voltage source in the PSpice Component and set the rising time lus, falling time /us, pulse width 100μs, low-side output voltage OV, and high-side output voltage 201 Use the load parts in the PSpice Component set resistor 50, and inductor 20mH in series. Use the thyristor in the ELEC4174_Fall_2023 library. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le a. Show your schematic. b. If we have voltage pulse (gate signal) appears at 15ms, 1) Plot the voltage across the resistor and voltage across the inductor. 2) Find the conduction angle (approximately) using results in part b.1). 3) Evaluate your plots in part b.1) for maximum value for VR and the point when V₁ across 0, briefly explain with words or equations what happened there.

5. Secondary choice of diode through cost considerations Look up your chosen diode on www.digikey.com. Suppose we make one bulk purchase and make all the bridge rectifiers we can out of it. How many circuits can we build, and how much do the diodes cost? Are there any cheaper alternatives that would still work? Provide cost estimates from the Digikey website. Digikey screenshots are needed here.

1) Generate the Ip vs Vps plots within the power supply limits of 0-3V, do this for gate- source voltages between zero and 3V spaced by 0.5 volts for both our default NFET and our PFET (W/L-5/0.5). This covers the full operating range of our devices. Label each trace with the VGs voltage used for each curve. For the NFET your plot should look qualitatively like this: 104 VGSI-VTH Saturation Region HLA-ESDA HLA-ESDA Vass Vosz Vast To do this you need to use a DC parameterized sweep with two loops, in one loop you are sweeping VDs and the other you are stepping VGs. To get the PFET characteristic to look like this you will need to change the signs of the some of the voltages and currents. b) Plots of the simulation results Repeat for the PFET Vos Careful: getting the PFET scans is trickier than you think, be sure that you cover the triode and saturation regions. (need the screenshots for these) Questions: For the NFET a) A legible copy of your simulation schematic, make sure it shows the device length and width a) For similar absolute values of the bias voltages the PFET and NFET drain currents are different, why? b) Observe how the slope of the curves in saturation change for different Vos. What does this imply about ro, the small signal output resistance as a function of Ves? c) What would the maximum current be if instead of a 5 micron wide device you had a 20 micron wide device?

To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).

Report Show that all transistors in the circuits operate properly and in the expected modes. Show that circuits can operate without distortion. Show the gain, and if possible, the BW of the circuits. Be prepared to discuss affects of the capacitors. Compare the two versions of the Op Amp. Explain why the various results differ, or if they do not differ, why they can differ.

Task 1: Three-phase half-wave diode rectifier with R load Recall Chapter 1, Make a new project. Build a three-phase half-wave diode rectifier with R load. Use the sinusoidal source in the SOURCE lib set amplitude 110V and frequency 60Hz. Use the diode and load parts in the PSpice Component set resistor 5.2. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le¹³. a. Show your analysis tab of simulation settings. b. Plot the load current. c. If we want to simulate an open circuit error happening at source phase a (0 deg shift) for this rectifier, 1) Show your modified schematic for this new simulation. 2) Plot the load current again. 3) Compare your answer for part c.2) with part b, briefly explain your plots.

2) Next generate a plot for Ip vs Vos for the diode connected NFET over 0-3 V of VDS bias. Include on your plot the effect of a bulk voltage of -0.5, 0, 0.5 and 1V. The easiest way to get all 3 curves on the same plot is to use 3 instances of the device in your simulation schematic, each with different bulk bias voltages. Using NET aliases can be useful here. Repeat for our PFET but now with bulk bias voltages of 3.5, 3, 2.5 and 2V. Here you should clearly see the body effect on the transistor characteristic. Replot these for the square root of ID vs VGs and estimate the effective threshold for each bulk voltage. For the NFET a) Schematic used for the simulation b) Plot showing the simulation results for ID vs VGs for the different bulk voltages. c) Plot of the square root of ID vs VGS for the different bulk voltages. d) A table showing the threshold voltages vs the bulk bias Then include the same for the PFET. (need the screenshots for these) General observations and suggestions: be sure you have a proper ground or the simulator will not work, it needs to be set as node zero. Setting the bias will be a challenge for many of you. Think about the meaning of the sign of the current. To make the PFET plots look "normal" you can change the signs of the voltages and currents plotted as appropriate. Use enough points in your simulation to make the curves look smooth. Note: clearly label the axes, label the traces with the Vgs or bulk bias voltages used, also make the traces thicker than the default and adjust colors for readability. Be careful in your choice of NFET3 or NFET4, only use the 3 terminal version if you are sure that the source voltage will always be at ground for the NFET. The NFET3 and PFET3 versions have their source and bulk terminals tied together internally. For our process this cannot be done for the NFET but it can for the PFET.

To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).

Pre-laboratory exercise 1. (2pts) For the summing amplifier in Fig. 1 with power supplies +7V, choose R2 to have Vout= -(Vini +2Vin2), if R1 R3 = 10KN. 2. (2pts) Use CIS Capture/Pspice to verify your hand-calculation and confirm that the circuit operates as a summing amplifier. For Vin1 use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC=1). For Vin2 use VDC source with a value of 2Vdc. Run a Time Domain (Transient) simulation profile for 2ms. 3. (2pts) For the differential amplifier in Fig. 2 with power supplies +7V, choose R1 to have Vout= (Vin2 - Vint), if R2 R3 R4 = 10K 4. (2pts) Use CIS Capture/Pspice to verify your hand-calculations and confirm that the circuit in Fig.2 operates as a differential amplifier. For Vin1 use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC-1). For Vin2 use VDC source with a value of 2Vdc. Run a Time Domain (Transient) simulation profile for 2ms. 5. (2pts) Use OrCAD Capture /Pspice to check the common-mode gain and CMRR for the circuit in Fig.2. For Vinl use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC-1). For Vin2 use VDC source with a value of 1Vdc. Run a Time Domain (Transient) simulation profile for 2ms. Use the cursors to find the common-mode gain and differential-mode gain then calculate CMRR.

Noninverting Amplifier (a) 2. The circuit for this step is the noninverting amplifier shown in Figure 12-11. Using the measured resistances from step 1, compute the closed-loop gain of the noninverting amplifier. The closed-loop gain equation is given in the text as Equation 12-8. Enter the computed value in Table 12-10. (e) (f) V₁= 500 mV 1.0 kHz Application Activity PROVE PERME (b) (c) Calculate your using the computed closed-loop gain. Record in Table 12-10. Change the circuit to the noninverting amplifier circuit shown in Figure 12- 11. Set the input for a 500 mVpp sine wave at 1.0 kHz with no dc offset. Record the measured setting in Table 12-10. (d) Measure the output voltage, Vor Record the measured value in Table 12-10. Measure the feedback voltage at pin 2. Record the measured value. Notice that the voltage at pin 2 is not near ground potential this time. Place a 1.0 M2 test resistor in series with the input from the generator. Observe the output voltage with the series resistor in place. You can think of the voltage change as being dropped across the test resistor, the rest is across the input resistance. You can use this to indirectly find the input resistance. Record the measured input resistance in Table 12-10. Table 12-10 +15 V HE 110μF 741C 44 10μ -15 V Figure 12-11 www 116 R₁ 10 k R₁ 1.0 kn Parameter Vin ACKNI) Vout Ve Rin Computed Measured Value Value 500 mVpp